1. Field of the Invention
This present invention relates to the provision of a chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, the invention is directed to the provision of unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
2. Discussion of the Prior Art
In the present state-of-the-art, methods are employed which facilitate the formation of a three-dimensional interconnect of multiple semiconductor die in order to be able to provide an enhanced performance, and to be able to reduce costs and excessive spending in leading-edge technology trends. At this time, various techniques are applied in order to be able to produce the closest proximity of circuitry on dissimilar or differently sized semiconductor chips, in order to thereby facilitate high performance interconnections, such as for processors and memories. In this connection, it is an aspect of the technology that three-dimensional semiconductor chips are fabricated through the use of packaging technology, such as wire bond die stacks, flip-chip stacks or combinations thereof; through the provision of through-silicon vias, wafer to wafer interconnects by means of wafer bonding; die-to-die interconnects by bump bonding or combinations thereof; and multiple die which are laminated into cubes with patterned interconnects located primarily along one or a single cube face.
However all of the foregoing methods currently employed are subject to drawbacks and limitations in the provision of methods and products, which facilitate the fabrication of edge connections for multi-level or three-dimensional semiconductor chips.
Pierson, et al., U.S. Pat. No. 6,156,165 disclose edge connections on integrated circuits or semiconductor chips, which extend along the length of the semiconductor chip edge. However, this disclosure is limited to primarily a method and fails to provide structure analogous to that claimed in the present invention. In this patent, chips with special edge connections are mounted on top of backplanes and may consist of a terminal wire or bond pad-like structure extending along the edge of a chip and a metalization or film which covers a terminal and bond pad by wrapping thereover along the entire edge of the chip and the surface below to some extent. This is a method of providing edge connections, which may be deemed unreliable in their utilization due to potential resistance, and electromigration issues potentially encountered at the corners of the wrapped around metalization and metal structure.
Angiulli, et al., U.S. Pat. No. 5,397,747, disclose a vertical chip mount memory package and method of producing therein semiconductor integrated circuit chips that are mounted directly on edge onto backplanes. Hereby, the edge connections depend on a dice cut through a solder ball which may be unreliable due to irregular solder ball cuts and also because of potential mechanical fatigue and high resistance and relying for the presence of solder, per se, in order to provide for the connections. Pursuant to the present invention, there is utilized an entirely different and repeatedly producible structure to provide for a connection which extends through the semiconductor or integrated circuit chip.
Malhi, et al., U.S. Pat. No. 5,031,072 and the continuation thereof, U.S. Pat. No. 5,031,072, describe primarily chip-in-slot in a backplane, an electrical connection being made to the semiconductor chips; however, which are not edge connections. The apparatus pursuant to the art utilizes topside connections and solder bridges to topside connections on a backplane, and has nothing in common with the present invention.